1. Field of the Invention
This invention generally relates to the field of a memory device with high charging voltage bit lines. More particularly, the present invention relates to a memory device with the pairs of bit lines, which can provide a higher voltage than the logical high voltage for the capacitors of the memory to save more electric charges.
2. Description of the Prior Art
A basic unit M of Dynamic Random Access Memory (DRAM) includes a transistor 12 and a capacitor 10, as shown in FIG. 1A. The logical status, 1 or 0, of the DRAM is decided by the capacitor 10. This is, the capacitor 10 can save a fixed amount of electric charges, and a full charging capacitor can be seen as logical 1, but an empty one represents logical 0. However, the capacitor 10 has a problem of leakage current, which results in the gradual loss of inner electric charges, so the electric charges cannot be kept on the original status. This situation makes the original logical status changed as time goes on. Therefore, the memory needs to be continuously charged during a period to temporarily hold the logical status and retain the accuracy in the logical status. Moreover, the memory cannot be read during the charging cycle. Reading data from the memory violates not only to the electric charges but also to the logical status. Hence, the DRAM needs to be refreshed (or to be written back or to be recharged) after every reading to keep the consistency of the contents. Therefore, the memory needs to be refreshed after not only a fixed period but also every reading.
As shown in FIG. 1B, each unit M of the DRAM represents one bit and has a unique address, which is assigned by a row address and a column address. The design of the unit M of the DRAM cannot be read alone in order to simplify the structure of the memory. Hence, many basic units of the DRAM are connected to the same Word Line (WL) and to the same Bit Line (BL) to form an array structure. Each array structure is connected to a sense amplifier via a pass gate to amplify the electric charges, which are read from (or written to) the basic units. Herein, the pass gate includes two N type transistors, N1 and N2. The sense amplifier includes two N type and two P type transistors, N3, N4, P1 and P2.
FIG. 1C illustrates the operation timings among the parts. The basic unit M of the memory has to be set in an active status before reading or writing, and this status is ended after a retaining period, as shown in region 14 of FIG. 1C. Pulling up the voltage of the WL to high voltage level turns on the transistor 12 of the memory basic unit M. Making the transistors, N1 and N2, of the pass gate turn on causes the logical status saved in the capacitor 10 of the memory basic unit M to be passed to the sense amplifier via a pair of BL and /BL. The voltage level of the pair of BL and /BL will be held at the original status, Vbleq, while the transistor 12 of the memory basic unit M is active. While there are electric charges in the capacitor 10, the voltage level of BL or /BL will increase as shown in 16 of FIG. 1C. On the contrary, while there are no any electric charges in the capacitor 10, the voltage level of BL or /BL will decrease. This is, the different logical status of the capacitor 10 causes different voltage of the bit lines. The voltage level of a connecting point NCS, which connects the transistors N3 and N4, decreases to a logical low level, Vss. The voltage level of a connecting point PCS, which connects the transistors P1 and P2, increases to a logical high level, Vblh. The voltage of the bit line with Vbleq level will decrease to the logical low level, Vss; the voltage of the bit line with higher than Vbleq level will increase to the logical high level, Vblh. As mentioned above, these processes are a procedure of memory writing back. Through the procedure, the logical status of the memory can retain the best logical level (Vblh, Vss).
The DRAM consumes much more power than other kinds of memory devices because of its continuous writing back processes. Thus, the development of the DRAM trends toward the low power to decrease the power consumption and the inner operation voltage of the DRAM has been reducing from 5V, 3.3V, 2.5V to 1.8V etc. The operation voltage of the bit lines also has the same development trend toward the low voltage. The quantity of electric charges Q saved in the capacitorQ=C* ΔV, wherein ΔV=Vblh−Vbleq
According to the formula, the quantity of electric charges Q in the capacitor will decrease while the operation voltage of the bit lines reduces and making the ΔV smaller. When the quantity of electric charges Q is decreasing, as shown in 16 of FIG. 1C, the differential voltage becomes smaller or the charging time is longer. Not only does the sense rate of the bit lines to the capacitors become slower but also the sense of logical status and the reliability of judgment also become poorer. Moreover, both the data retention time and the writing back cycle also become shorter.
Toward the development trend of the low operation voltage of the DRAM, the problems of how to keep the sense rate of the bit lines, how to retain the reliability of the logical sense and how to hold the data retention time are necessary to be overcome.